`timescale 1ns / 1ps
`include "defines.v"

module inst_rom(

	input wire ce,
	input wire [`InstAddrBus] addr,
	output reg [`InstBus] inst
	
);

	reg[`InstBus]  inst_mem[127:0];

	initial $readmemh ( "E:/vivado workplace/inst_rom.data", inst_mem );

	always @ (*) begin
		if (ce == `ChipDisable) begin
			inst <= `ZeroWord;
	  end else begin
		  inst <= inst_mem[addr[31:2]];
		end
	end

endmodule